WebM's G2 VP9 Decoder IP is the latest addition to our family of hardware IP products for multimedia system-on-chip designs. G2 is the first decoder IP to implement VP9 in hardware, delivering next-generation performance and power efficiency, and enabling up to 4K (2160p 60FPS) resolution playback on smart TVs, PCs and post-PC consumer devices.
As with our VP8 hardware IPs, G2 is currently available to semiconductor companies having firm plans to ship VP9-supporting products. A written, no-cost agreement is required. Please complete the form here to learn more.
The G2 VP9 decoder uses a completely new hardware architecture. A majority of its hardware modules are designed in C++ and converted to RTL using Calypto's Catapult C high-level synthesis tool. This higher abstraction level makes design implementation and verification much faster and cleaner than in a traditional RTL design flow. Nevertheless, G2's top level is hand-written RTL, making IP integration straightforward.
This G2 block diagram depicts the new architecture:
SoC-level integration of G2 is done in the same way as our VP8 IP products. G2 integrates into AXI bus architecture, implementing the advanced transaction features introduced in the AXI 4.0 specification. All required SRAM instances are combined under a single SRAM wrapper for ease of integration.
G2 includes a simple API to integrate the decoder into common multimedia frameworks such as Android MediaCodec, V4L2, OpenMAX and others. Accompanying software and driver code is very lightweight, and the load on host CPUs is insignificant -- regardless of content bitrate or resolution.
G2 supports the following features:
WebM G2 enables 4K (2160p) playback on high-end consumer devices. The design is scalable to meet up to 2160p@60fps decode requirements with a single core, minimizing the silicon area and decoding latency. While actual performance is dictated by the target SoC design parameters, here are a few G2 key parameters:
* Zero-latency clock frequency requirement tells you the ideal performance of the decoding pipeline itself, i.e., DRAM access latencies are not taken into account. Third-party VP9 decoder hardware implementors are encouraged to meet the WebM VP9 hardware decoder speed.
** Frames per second performance depends on the actual decoder clock frequency of the final SoC.
The standard G2 delivery package includes all required source code to integrate the decoder with the actual SoC.