The WebM VP8 video hardware IP designs support encoding and decoding WebM/VP8 video up to 2160p (4k) resolution. Implemented as RTL source code (VHDL or Verilog), both VP8 IP designs are currently available to semiconductor companies having firm plans to ship VP8-supporting products. A written, no- cost agreement is required. Please complete the form here to learn more.
Intended for chipsets and ASICs targeting multimedia devices (HD set-top boxes, mobile devices, netbooks, webcams, etc.), the WebM encoder and decoder hardware IP is built on technology developed by Google’s Oulu, Finland office. This group has developed silicon-proven designs deployed in hundreds of millions of chips worldwide, and provides semiconductor manufacturers with a minimal-risk solution for integrating WebM video capability with their chipsets.
The designs have not been optimized for FPGA, and can typically reach only SD resolution performance due to maximum clock frequency limitations. Licensee- contributed FPGA optimizations are especially welcome.
Implementors: Please see the RTC Hardware Coding Requirements document for important information about real-time communications support.
Multi-format RTLs Commercial multi-format RTLs are also available for use with the WebM designs. Please contact Verisilicon for more information.