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The WebM video hardware IP designs support encoding and decoding WebM/VP8 video up to 1080p resolution. Implemented as RTL source code (VHDL or Verilog), both WebM IP designs are currently available to semiconductor companies having firm plans to ship VP8-supporting products. A written, no-cost agreement is required. Please complete the form below to find out more.

Intended for chipsets and ASICs targeting multimedia devices (HD set-top boxes, mobile devices, netbooks, webcams, etc.), the WebM encoder and decoder hardware IP is built on technology developed by Google's Oulu, Finland office. This group has developed silicon-proven designs deployed in hundreds of millions of chips worldwide, and provides semiconductor manufacturers with a minimal-risk solution for integrating WebM video capability with their chipsets.

The designs have not been optimized for FPGA, and can typically reach only SD resolution performance due to maximum clock frequency limitation. Licensee-contributed FPGA optimizations are especially welcome.

Deliverables

• RTL source code (VHDL or Verilog) with RTL test bench and test data.
• ANSI C source code for hardware drivers, with software test bench and test data.
• Technical documentation: hardware and software integration guides and application programming interface (API) manuals.
• Reference C-model (bit-accurate with RTL).

WebM Video Decoder Hardware IP

Maturity

• Silicon-proven, in mass production in several chipsets (e.g. Rockchip RK2918).

Details

• Design model number G-Series 1 (version 4, "Driver").
• Requires less than 100 MHz clock frequency to decode 1080p video at 30 fps, and can achieve 60 fps.
• Full hardware acceleration; < 2 MHz CPU load on ARM9 or equivalent for 1080p at 30 fps.
• Input data: VP8 bitstream
• Output data: YCbCr 4:2:0 semi-planar video data
• Supports unlimited multi-channel decoding, enabling simultaneous playback of more than ten SD video streams on the same chip.
• Includes pre-fetching and buffering mechanisms to ensure high latency tolerance for smooth operation with Network-on-Chip architectures or low-end DRAMs
• The logic consumes less than 25 milliwatts of power for 1080p video decoding and less than 5 milliwatts for 480p (TSMC65nm LP)

Silicon Utilization and Integration

• Silicon area: 357 kGates logic, 52 kBytes single-port SRAM.
• Simple design: single clock domain; only rising clock edge used; no multicycle paths.
• Choose internal memory size according to resolution requirements, from QCIF to 1080p.
• Bus protocol interfaces: AHB, AXI and APB.
• Maximum synthesizable clock frequency: 310 MHz (TSMC65nm LP, no wireload)

WebM Video Encoder Hardware IP

Maturity

• Several tape-outs, proven in FPGA. First demonstrated at MWC 2011, Barcelona.

Details

• Design model number H-Series 1 (version 4, "Dragonfly").
• Encoder requires less than 270MHz clock frequency to encode 1080p video at 30 fps.
• Full hardware acceleration, < 1 MHz CPU load on ARM9 or equivalent for 1080p at 30 fps. Supports ultra low-end MCUs such as 8051 as controller.
• Input data: YCbCr 4:2:0, 4:2:2 or RGB. Preprocessor performs cropping, rotation, stabilization and color conversion.
• Output data: VP8 bitstream
• Supports unlimited multi-channel encoding, at the same or different resolutions, making it suitable for simulcast.
• Consumes less than 80 milliwatts for HD video encoding and less than 20 milliwatts for SD (TSMC 65 nm LP).

Silicon Utilization and Integration

• Silicon area: 988 kGates logic, 172/112 kBytes single-port SRAM (max/min search area configuration).
• Simple design: single clock domain; only rising clock edge used; no multicycle paths.
• Choose internal memory size according to resolution requirements, from QCIF to 1080p.
• Bus protocol interfaces: AHB, AXI and APB.

Request Source Code

Please provide the information requested below. We will reply via email with further details on completing the license and acquiring the source.